
R
Termination and Transmission Line Summaries
Table 5-4:
QDRII SRAM Terminations
Signal
Write Data (D)
Read Data (Q)
Write Strobe (K, K)
Read Strobe (CQ, CQ)
Clock (CK, CK)
FPGA Driver
HSTL_I_18
HSTL_I_DCI_18
HSTL_I_18
HSTL_I_DCI_18
HSTL_I_18
Termination at FPGA
No termination
No termination
No termination
No termination
No termination
Termination at Memory
50 Ω pull-up to 0.9V
No termination
50 Ω pull-up to 0.9V
No termination
100 Ω differential termination
between pair
Address (A, BA)
HSTL_I_18
No termination
50 Ω pull-up to 0.9V after the last
component
Control (RAS, CAS, WE,
CS, CKE, and BW)
HSTL_I_18
No termination
50 Ω pull-up to 0.9V after the last
component
Table 5-5:
RLDRAM II Terminations
Signal
Data (DQ for CIO)
Data (Q for SIO)
Write Data (D for SIO)
Write Strobe (DK, DK)
FPGA Driver
HSTL_II_DCI_18
HSTL_I_DCI_18
HSTL_I_18
DIFF_HSTL_I_18
Termination at FPGA
No termination
No termination
No termination
No termination
Termination at Memory
50 Ω pull-up to 0.9V
No termination
50 Ω pull-up to 0.9V
100 Ω differential termination
between pair
Read Strobe (QK, QK)
DIFF_HSTL_II_DCI_18 (for CIO)
No termination
No termination
DIFF_HSTL_I_DCI_18 (for SIO)
Data Valid (QVLD)
HSTL_II_DCI_18 (for CIO)
No termination
No termination
HSTL_I_DCI_18 (for SIO)
Clock (CK, CK)
DIFF_HSTL_I_18
No termination
100 Ω differential termination
between pair
Address (A, BA)
HSTL_I_18
No termination
50 Ω pull-up to 0.9V after the last
component
Control (RAS, CAS, WE,
CS, and CKE)
Virtex-5 FPGA ML561 User Guide
HSTL_I_18
No termination
50 Ω pull-up to 0.9V after the last
component
49
UG199 (v1.2.1) June 15, 2009